RISC:-
The Reduced Instruction Set Computer (RISC) is a microprocessor CPU design philosophy which supports a simpler set of instructions all of which take the same amount of time to execute. Some RISC microprocessors are AVR, PIC, DEC Alpha, SPARC, MIPS, and IBM's PowerPC.
Why RISC was created?
Traditional CPUs had many features that facilitated easier coding but were left unused. The main problem here was that these features took a long time to be executed.
Earlier, when compiler technology was absent, programming was done at the hardware level using machine code or assembly. This led to the creation of complex or complicated instructions that were actually only a representation of high level functions in the high-level languages. It was considered easy to program at hardware level than to write a compiler which lead to complexity in the CPUs.
Memory was limited and slow at that time. The whole system did not have more than a few kilobytes. This raised the need to keep information at a high density of closeness in computer programs. This was beneficial for such memory as it reduced the access time.
Since CPUs had only a few registers as internal CPU register bits were expensive and more instructions were required to work with them, hence reducing speed. This made it necessary for CPU makers and designers to build instructions that could do the maximum possible work.
The above led to what is now called Complex Instruction Set Computer (CISC) philosophy.
RISC came on the horizon in the 1970s when certain things were found out. One of this was the paradox that a particular operation worked slower than a number of smaller operations achieving the same functionality. This was due to the fact that CPU designers only used the most-used operations as they were limited by time to deliver. Also, newer CPUs were way faster than the memory they worked with. This meant that as CPUs become more faster, more registers would be needed to handle such higher operational frequencies.
Under RISC, instead of using a single overly complex instruction, a series of simple instructions was used to achieve the same thing. Such simple instructions left more space and reduced the need to store data in the registers as it could now be carried alongwith the instructions. This also made the memory interface simple.
RISC allows CPU designers to:
* increase the size of the register set
* increase internal parallelism
* increase the size of caches (introduced later)
* add more functions
Development Cycle of RISC
The first actual RISC machine was CDC 6600 supercomputer, designed in 1964 by Jim Thornton and Seymour Cray. The CDC 6600 sported a load-store architecture and eleven pipelined functional units for arithmetic and logic.
Data General Nova minicomputer, designed in 1968, was another load-store architecture based machine.
UC Berkeley's RISC project was initiated in 1980 leas by David Patterson that used pipelining to gain higher performance. It used a thing called register windows that limited the CPUs 128 registers to the set of 8 registers that could be used at a time. This translated into faster time and higher performance.
RISC-I processor came out 1982 from this project. It had only 44,420 transistors in contrast to the CISC ones that had 100000 on an average at that time and it had only 32 instructions. Surprisingly, it won over any other single-chip design in performance. Comprised off 40,760 transistors and 39 instructions, RISC-II came out in 1983 and was over 3 times faster than RISC-I.
IBM started developing a chip-based RISC CPU 1975 that led to ROMP in 1981, which means Research (Office Products Division) Mini Processor. In 1986, when it was released on the RT-PC, it proved to be a failure in the light of the fact that it was not a good performer.
Sun Microsystems developed the SPARC with the help of RISC-II. It showed how the advantages of RISC were real. IBM developed the POWERPC, which is now the most used RISC chips.
Today, RISC chips are used almost in all machines, the best example being cars where even 10 of such chips may be used. The desktop PC scenario, however, uses Intel’s x86 architecture.
CISC:-
A Complex instruction set computer (CISC) is a microprocessor instruction set architecture in which each instruction executes several low-level operations. These operations maybe an arithmetic operation or a memory store or retrieval. The term was coined to differentiate between it and the Reduced Instruction Set Computer (RISC).
Development of CISC
There was no official start of the development of the CISC. It was more of an industry trend that prevailed before the RISC processors were designed. Compilers were not present at that time. This forced the developers to write instruction sets that could support high level languages. This was basically a semantics gap. They made complex addressing modes and clubbed them together to form one single instruction. This clubbing resulted in small programs sizes and reduced the number calls to main memory that caused a tremendous savings on the cost of a computer in the 1960s.
Problems in the CISC
There were certain problems that were later discovered that finally led to the development of RISC. These were:
* CISC allowed high-level languages to express their constructs in a few instructions. This was achieved easily. The problem was that this did not translate into better or improved performance each time. It was found out that it was possible to increase performance by using a series of simple and multiple instructions instead of a single and complex one on some processors.
* The complex instruction also meant greater execution time. The overhead that was the result of the complexity of an instruction took up more and more time and silicon. As a result, even simple instructions were slow to execute due to the presence of the complex ones.
* The CISC architecture resulted in the use of many transistors on the chip. This left very less or no space for other techniques of improving performance.
* Another implication of the CISC was that it took the chip maker a lot of time and effort to develop it.
There are certain examples of CISC processors such as the System/360, VAX, PDP-11, Motorola 68000 range of processors etc.
Difference between CISC and RISC:-
The differences between CISC and RISC architectures are as follows:
* While CISC gave an emphasis to hardware in order to reduce the complexity of the high level languages, the RISC architecture concentrated on software and kept the hardware as simple as possible.
* The CISC architecture includes multi-clock complex instructions to do the processing while the RISC architecture uses the Single-clock, reduced instruction to do so.
* The CISC architecture used the memory-to-memory way of working. The instructions like LOAD from memory and STORE in memory were kept together other instructions to form a single, complex instruction. RISC, on the other hand, used Register-to-Register and both of the above instructions were independent of each other.
* The CISC architecture was able to achieve small program size due to the clubbing of many instructions into one and had a high number of cycles per second. This lead to high speeds but was not always true. The use of RISC resulted in larger programs and a lower number of cycles in each second.
* The CISC architecture stored the complex instructions that it had in the transistors while the RISC architecture used the transistors to store memory registers.